- 6510 (NMOS version)
- CPU with 6 Bit data port, this is a modified 6502 CPU with a 6 pin I/O port and tri-state data and address bus, the I/O port is mainly used for Tape I/O and for memory page selection
The 8500 will access the bus while Phi2 is High, allowing the video chip to uses the bus while Phi2 is low.
While Phi2 or AEC is low, the address and data bus is tri-stated by the 8500.
the AEC line is used by the video chip when it needs more time to handle sprites or any external device on the expansion port that want to perform direct memory access (DMA) like memory expansions.
Before the AEC may be lowered, the BA should be low for at least 3 cycles.
When the BA line is low the 8500 will finish the current command (max 3 cycles) and will wait for the BA to go high again.
- Commodore 64
2 thoughts to “8500”
In the image, signals on pins 38 and 39 are wrong: Pin 38 should be R/W, pin 39 should be Phi2.
Thank you, I will fix the error, also on the 6510.