- 8500 (HMOS version)
- CPU with 6 Bit data port, this is a modified 6502 CPU with a 6 pin I/O port and tri-state data and address bus, the I/O port is mainly used for Tape I/O and for memory page selection
The 6510 will access the bus while Phi2 is High, allowing the video chip to uses the bus while Phi2 is low.
While Phi2 or AEC is low, the address and data bus is tri-stated by the 6510.
the AEC line is used by the video chip when it needs more time to handle sprites or any external device on the expansion port that want to perform direct memory access (DMA) like memory expansions.
Before the AEC may be lowered, the RDY should be low for at least 3 cycles.
When the RDY line is low the 6510 will finish the current command (max 3 cycles) and will wait for the RDY to go high again.
- Commodore 64
2 thoughts to “6510”
“Before the AEC may be lowered, the BA should be low for at least 3 cycles.”
– that should read “the RDY should be low for at least 3 cycles.”: the 6510 doesn’t have a BA pin: that’s an output line from the C64’s VIC chip which feeds the the 6510’s RDY line.
You’re right, I changed the text.